Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
One important process requiring careful inspection is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (i.e., a photoresist layer) which has been previously coated on a layer, such as a polysilicon or metal layer, formed on the silicon wafer. The transfer of the mask pattern onto the photoresist layer is conventionally performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. The design rule limitation is referred to as the critical dimension (“CD”), defined as the smallest width of a line or the smallest space between two lines permitted in the fabrication of the device. The CD for most ultra large scale integration applications is on the order of a fraction of a micron.
A related process where CD is crucial is known as “resist trim”. As those skilled in the art will appreciate, photolithography employing light to expose sub-micron features on a photoresist layer is very costly and complicated. Moreover, as desired feature line widths become smaller, the limits of the photolithographic process are frequently exceeded. For example, 50-70 nanometer line widths are becoming commonplace, but photolithographic processes are typically capable of producing line widths no smaller than 100-120 nanometers. Thus, techniques have been developed to use photolithograpy equipment to expose features that are larger than desired, then follow this exposure with a process called a resist trim to “shrink” the exposed features to their final size. Photoresist trim extends lithography capabilities by using a plasma etch step that can physically reduce the printed photoresist CD by up to 30 percent. Specifically, after the oversized features are exposed and the photoresist developed, the wafer is brought to an etch chamber, and a specifically designed “resist etch step” is carried out, typically an isotropic etch step that shrinks the size of the developed resist feature. The actual feature (e.g., a polysilicon gate or metal line) is thereafter etched, typically using a different etch recipe in the same or in a different etch chamber.
As design rules shrink and process windows (i.e., the margins for error in processing) become smaller, inspection and measurement of surface features' CD, as well as their cross-sectional shape (“profile”) are becoming increasingly important. Deviations of a feature's CD and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature's CD and profile may indicate processing problems, such as stepper defocusing or photoresist loss due to over-exposure.
One method for monitoring and correcting CD variations is performed by selecting one or more test wafers from a lot of wafers whose photoresist has been exposed and developed to create larger-than-desired features, and measuring a representative photoresist feature CD from the test wafers, as with a critical dimension scanning electron microscope (CD-SEM). The wafers are then processed through a photoresist etch step and a gate etch step, and the CD of the etched feature is measured. The results of the initial and final CD measurements are then used to adjust the etch recipe for the remaining wafers in the lot to drive their CDs to target values. According to conventional CD monitoring techniques, measuring CDs of sample wafers (i.e., initially measuring photoresist features formed on the wafers and then measuring gates) is done off-line at a SEM, and the CD of a particular feature on a wafer is not used to decide what etch recipe is used for processing that wafer. Furthermore, feature profile is not measured or taken into account when adjusting the etch recipe according to conventional techniques. For further information regarding prior art techniques, the reader is directed to, for example, U.S. Pat. No. 5,926,690 to Toprac et al.
As Advanced Process Control (APC) is gaining widespread adoption with semiconductor manufacturers, semiconductor equipment manufacturers are coming under increasing pressure to provide integrated process control solutions. With feature sizes shrinking below 130 nm, the need for very tight process tolerances and the need for productivity improvement from the billion-plus dollar factories are driving the need for APC.
There exists a need for a simple, cost-effective methodology for fast and meaningful identification and correction of CD and profile variation without significantly reducing production throughput or yield. There also exists a need for a robust and efficient apparatus and methodology for accurately carrying out resist trim and etch operations.